Most high speed analog to digital converter (ADC) architectures have a bank of comparators that have thresholds spaced over the range of the analog signal to be converted. The outputs of a bank of comparators are ideally all ones for those comparators which have thresholds below the current value of the analog input and all zeroes for those with thresholds above the analog input, as discussed in Behzad Razavi, Principles of Data Conversion System Design, pp. 101-116, IEEE Press, New York (1995). After the bank of comparators, an encoder is commonly used to encode the output of the comparators into a code, such as a binary or gray code. One class of prior art encoders uses either a ROM structure or a collection of logic gates to encode the comparator outputs to a desired code.
There can be either static or dynamic errors in the thresholds of the comparators such that there is not always a single well defined transition from all ones to all zeros, so a relatively complex gate structure with three or more inputs is generally needed to ensure a suitably high probability of encoding the proper code from the comparator outputs. This in turn means either that each comparator output has a fanout of three or more, or that a cascaded gate structure is needed. Neither of these is desirable for high speed and low power. Other approaches include a cascade of exclusive-or gates, or an adder tree that simply sums the number of comparators with high outputs. Both of these approaches also involve a relatively high number of gates and high power dissipation.
FIG. 1 shows the encoding of a bank of 7 comparator outputs C1 to C7 into a 3 bit gray code (G3, G2 and G1) or a 3 bit binary code (B3, B2 and B1). The 7 comparator outputs are selected so that if comparator output Cw, wherein w ranges from 1 to 2**N−1 and wherein N is the number of bits in the encoded code, is a binary zero, then each comparator output numbered Cx wherein x is greater than w, is binary zero. The thresholds of each comparator are also selected so that if comparator output Cy, wherein y ranges from 1 to 2**N−1 and wherein N is the number of bits in the encoded code, is binary one, then each comparator output numbered Cz wherein z is less than y, is binary one. For example, in FIG. 1 when comparator output C4 is binary 0, then comparator outputs C5 through C7 are also binary zero. When comparator output C4 is binary 1, then comparator outputs C1 through C3 are also binary one.
The comparator outputs C1 to C7 may be encoded into a 3-bit gray code or a 3-bit binary code by using logic. Using the notation that the complement of a signal “A” is “AX” (not A=AX), the logic equations for the encoders can be implemented with the following logic.
For the binary code the encoding logic by inspection from FIG. 1 is:B1=C1*C2X+C3*C4X+C5*C6X+C7B2=C2*C4X+C6B3=C4.
For the gray code the encoding logic by inspection from FIG. 1 is:G1=C1*C3X+C5*C7X G2=C2*C6X G3=C4.
FIG. 2 shows one example of a prior art binary encoder for implementing the logic for B1, B2 and B3. This prior art encoder has a relatively complex gate structure and has a cascaded gate structure, which is not desirable for high speed and low power.
Differential current-steering series-gated logic circuitry is recognized as one of the faster types of circuitry for implementing logic functions. It is commonly implemented with either bipolar or FET integrated circuits. A basic circuit for a design is a binary current steering tree, made of one differential pair or more generally, a binary current steering switch on the bottom level, connected to two differential pairs on the second level. The two differential pairs are in turn connected to four differential pairs on the third level, and so on to form an N level current steering circuit with 2N−1 differential pairs on the N-th level.
C. S. Choy in “Minimization technique for series-gated emitter-coupled logic”, IEEE Proceedings, Vol. 136, Pt. G, No. 3, June 1989, describes a technique for deriving an optimized multi-level current steering gate for differential logic given logic equations or a truth table, the contents of which are incorporated by reference.
What is needed are encoders and methods of making encoders that have high speed and low power. The embodiments of the present disclosure answer these and other needs.